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cy14b104l, cy14b104n 4 mbit (512k x 8/256k x 16) nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-07102 rev. *k revised november 26, 2008 features 20 ns, 25 ns, and 45 ns access times internally organized as 512k x 8 (cy14b104l) or 256k x 16 (cy14b104n) hands off automatic store on power down with only a small capacitor store to quantumtrap ? nonvolatile elements initiated by software, device pin, or autostore ? on power down recall to sram initiated by software or power up infinite read, write, and recall cycles 200,000 store cycles to quantumtrap 20 year data retention single 3v +20 % to ?10 % operation commercial and industrial temperatures 48-ball fbga and 44/54-pin tsop - ii packages pb-free and rohs compliance functional description the cypress cy14b104l/cy14b104n is a fast static ram, with a nonvolatile element in each memory cell. the memory is organized as 512k bytes of 8 bits each or 256k words of 16 bits each. the embedded nonvolatile elements incorporate quantumtrap technology, producing the world?s most reliable nonvolatile memory. the sram provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. 67$7,&5$0 $55$< ; 5 2 : ' ( & 2 ' ( 5 &2/801,2 &2/801'(& , 1 3 8 7 % 8 ) ) ( 5 6 32:(5 &21752/ 6725(5(&$// &21752/ 4xdwuxp7uds ; 6725( 5(&$// 9 && 9 &$3 +6% $ $ $ $ $ $ $ $ 62)7:$5( '(7(&7 $ $ 2( &( :( %+( %/( $ $ $ $ $ $ $ $ $ $ $ '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 logic block diagram [1, 2, 3] note 1. address a 0 - a 18 for x8 configuration and address a 0 - a 17 for x16 configuration. 2. data dq 0 - dq 7 for x8 configuration and data dq 0 - dq 15 for x16 configuration. 3. bhe and ble are applicable for x16 configuration only. [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 2 of 25 pinouts figure 1. pin diagram - 48 fbga figure 2. pin diagram - 44 pin tsop ii we v cc a 11 a 10 v cap a 6 a 0 a 3 ce nc nc dq 0 a 4 a 5 nc dq 2 dq 3 nc v ss a 9 a 8 oe v ss a 7 nc nc nc a 17 a 2 a 1 nc v cc dq 4 nc dq 5 dq 6 nc dq 7 nc a 15 a 14 a 13 a 12 hsb 3 2 6 5 4 1 d e b a c f g h a 16 a 18 nc dq 1 48-fbga (not to scale) top view (x8) [4] [5] we v cc a 11 a 10 v cap a 6 a 0 a 3 ce dq 10 dq 8 dq 9 a 4 a 5 dq 13 dq 12 dq 14 dq 15 v ss a 9 a 8 oe v ss a 7 dq 0 bhe nc a 17 a 2 a 1 ble v cc dq 2 dq 1 dq 3 dq 4 dq 5 dq 6 dq 7 a 15 a 14 a 13 a 12 hsb 3 2 6 5 4 1 d e b a c f g h a 16 nc nc dq 11 48-fbga (not to scale) top view (x16) [4] [5] notes 4. address expansion for 8 mbit. nc pin not connected to die. 5. address expansion for 16 mbi t. nc pin not connected to die. 6. hsb pin is not available in 44-tsop ii (x16) package. nc a 8 nc nc v ss dq 6 dq 5 dq 4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 a 17 a 18 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii top view (not to scale) a 10 nc we dq 7 hsb nc v ss v cc v cap nc (x8) [4] [5] v ss dq 6 dq 5 dq 4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 ble a 9 ce a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 11 a 10 a 14 bhe oe a 15 a 16 a 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii top view (not to scale) we dq 7 a 0 v ss v cc dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 v cap (x16) 44-tsop ii (x16) 44-tsop ii (x8) [6] [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 3 of 25 figure 3. pin diagram - 54 pin tsop ii (x16) pin definitions pin name io type description a 0 ? a 18 input address inputs used to select one of the 524,288 bytes of the nvsram for x8 configuration . a 0 ? a 17 address inputs used to select one of the 262,144 words of the nvsram for x16 configuration . dq 0 ? dq 7 input/output bidirectional data io lines for x8 configuration . used as input or output lines depending on operation. dq 0 ? dq 15 bidirectional data io lines for x16 configuration . used as input or output lines depending on operation. we input write enable input, active low . when selected low, data on the io pins is written to the specific address location. ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. io pins are tri-stated on deasserting oe high. bhe input byte high enable, active low . controls dq 15 - dq 8 . ble input byte low enable, active low . controls dq 7 - dq 0 . v ss ground ground for the device . must be connected to the ground of the system. v cc power supply power supply inputs to the device . hsb [6] input/output hardware store busy (hsb ) . when low this output indicates that a hardware store is in progress. when pulled low external to the chip it initiates a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional ). after each store operation hsb will be driven high for short time with standard output high current. v cap power supply autostore capacitor . supplies power to the nvsram during power loss to store data from sram to nonvolatile elements. nc no connect no connect . this pin is not connected to the die. pinouts (continued) a 17 dq 7 dq 6 dq 5 dq 4 v cc dq 3 dq 2 dq 1 dq 0 nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 v cap we a 8 a 10 a 11 a 12 a 13 a 14 a 15 a 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 54 - tsop ii top view ( not to scale) oe ce v cc nc v ss nc a 9 nc nc nc nc nc nc 54 53 52 51 49 50 hsb bhe ble dq 15 dq 14 dq 13 dq 12 v ss dq 11 dq 10 dq 9 dq 8 (x16) [4] [5] [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 4 of 25 device operation the cy14b104l/cy14b104n nvsram is made up of two functional components paired in the same physical cell. they are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to the sram (the recall operation). using this unique arch itecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14b104l/cy14b104n supports infinite reads and writes similar to a typical sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 200k store operations. see the ?truth table for sram operations? on page 15 for a complete description of read and write modes. sram read the cy14b104l/cy14b 104n performs a read cycle when ce and oe are low and we and hsb are high. the address specified on pins a 0-18 or a 0-17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each are accessed. byte enables (bhe , ble ) determine which bytes are enabled to the output, in the case of 16-bit word s. when the read is initiated by an address transition, the output s are valid after a delay of t aa (read cycle 1). if the r ead is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data output repeatedly responds to address changes within the t aa access time without the need fo r transitions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycle. the data on the common io pins dq 0?15 are written into the memory if the data is valid t sd before the end of a we controlled write or bef ore the end of an ce controlled write. the byte enable inputs (bhe , ble ) determine which bytes are written, in the case of 16bit words. it is recommended that oe be kept high duri ng the entire write cycle to avoid data bus contention on common io lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b104l/cy14b104n stores data to the nvsram using one of the following three storage operations: hardware store activated by hsb; software store activated by an address sequence; autostore on device power down. the autostore operation is a unique feature of quantumtrap technology and is enabled by default on the cy14b104l/cy14b104n. during a normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 4 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to dc electrical characteristics on page 7 for the size of v cap . the voltage on the v cap pin is driven to v cc by a regulator on the chip. a pull up should be placed on we to hold it inactive during power up. this pull up is only effective if the we signal is tri-state during power up. many mpu?s will tri-state their controls on power up. this should be verified when using the pull up. when the nvsram comes out of power-on-re call, the mpu must be active or the we held inactive until the mpu comes out of reset. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiat ed store cycles are performed regardless of whether a write operation has taken place. the hsb signal is monitored by the syst em to detect if an autostore cycle is in progress. figure 4. autostore mode hardware store operation the cy14b104l/cy14b104n provides the hsb [6] pin to control and acknowledge the store operations. use the hsb pin to request a hardware store cycle. when the hsb pin is driven low, the cy14b104l/cy14b104n conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the cy14b104l/cy14b104n contin ues sram operations for t delay . if a write is in progress when hsb is pulled low it is enabled a time, t delay to complete. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. in case the write latch is not set, hsb will not be driven low by the cy14b104 l/cy14b104n but any sram read/write cycles are inhibited until hsb is returned high by mpu or other external source. during any store operation, regardless of how it is initiated, the cy14b104l/cy14b104n continues to drive the hsb pin low, releasing it only when the store is complete. upon 0.1uf vcc 10kohm v cap vcc we v cap v ss [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 5 of 25 completion of the store operation, the cy14b104l/cy14b104n remains disabled until the hsb pin returns high. leave the hsb unconnected if it is not used. hardware recall (power up) during power up or after any low power condition (v cc cy14b104l, cy14b104n document #: 001-07102 rev. *k page 6 of 25 preventing autostore the autostore function is disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore is re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled, a manual store operation (hardware or software) must be issued to save the autostore state through su bsequent power down cycles. the part comes from the factory with autostore enabled. data protection the cy14b104l/cy14b104n protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc < v switch . if the cy14b104l/cy14b104n is in a write mode (both ce and we are low) at power up, after a recall or store, the write is inhibited until the sram is enabled after t lzhsb (hsb to output active). this protects against inadvertent writes during power up or brown out conditions. noise considerations refer to cy application note an1064 . l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [8, 9] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [8, 9] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [8, 9] table 1. mode selection (continued) ce we oe, bhe , ble [3] a 15 - a 0 [7] mode io power [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 7 of 25 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c maximum accumulated storage time ............at 150 c ambient temperature........................1000h ............at 85 c ambient temperature..................... 20 years ambient temperature with power applied ............................................ ?55 c to +150 c supply voltage on v cc relative to gnd ..........?0.5v to 4.1v voltage applied to outputs in high-z state....................................... ?0.5v to v cc + 0.5v input voltage...........................................?0.5v to vcc + 0.5v transient voltage (<20 ns) on any pin to ground potentia l ............ ...... ?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount pb soldering temperature (3 seconds) .......................................... +260 c dc output current (1 output at a time, 1s duration).... 15 ma static discharge voltage....... ........... ............ ............ > 2001v (per mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v to 3.6v industrial ?40 c to +85 c 2.7v to 3.6v dc electrical characteristics over the operating range (v cc = 2.7v to 3.6v) parameter description test conditions min max unit i cc1 average v cc current t rc = 20 ns t rc = 25 ns t rc = 45 ns values obtained without output loads (i out = 0 ma) commercial 65 65 50 ma ma ma industrial 70 70 52 ma ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max average current for duration t store 10 ma i cc3 [10] average v cc current at t rc = 200 ns, 3v, 25c typical all i/p cycling at cmos levels. values obtained without output loads (i out = 0 ma). 35 ma i cc4 average v cap current during autostore cycle all inputs don?t care, v cc = max average current for duration t store 5ma i sb v cc standby current ce > (v cc ? 0.2). all others v in < 0.2v or > (v cc ? 0.2v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz. 5ma i ix [11] input leakage current (except hsb ) v cc = max, v ss < v in < v cc ?1 +1 a input leakage current (for hsb ) v cc = max, v ss < v in < v cc ?100 +1 a i oz off-state output leakage current v cc = max, v ss < v out < v cc , ce or oe > v ih or bhe /ble > v ih or we < v il ?1 +1 a v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap [12] storage capacitor between v cap pin and v ss , 5v rated 61 180 f notes 10. typical conditions for the active curre nt shown on the dc electrical characterist ics are average values at 25c (room temper ature), and v cc = 3v. not 100% tested. 11. the hsb pin has i out = -2 ua for v oh of 2.4v when both active high and low drivers are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. 12. v cap (storage capacitor) nominal value is 68uf. [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 8 of 25 ac test conditions input pulse levels ....................................................0v to 3v input rise and fall times (10% - 90%) ........................ < 3 ns input and output timing reference levels .................... 1.5v data retention and endurance parameter description min unit data r data retention 20 years nv c nonvolatile store operations 200 k capacitance in the following table, the capacitance parameters are listed. [13] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0v 7pf c out output capacitance 7 pf thermal resistance in the following table, the thermal resistance parameters are listed. [13] parameter description test conditions 48-fbga 44-tsop ii 54-tsop ii unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 28.82 31.11 30.73 c/w jc thermal resistance (junction to case) 7.84 5.56 6.08 c/w figure 5. ac test loads 3.0v output 5 pf r1 r2 789 3.0v output 30 pf r1 r2 789 for tri-state specs 577 577 13. these parameters are guaranteed but not tested. [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 9 of 25 ac switching characteristics parameters description 20 ns 25 ns 45 ns unit cypress parameters alt parameters min max min max min max sram read cycle t ace t acs chip enable access time 20 25 45 ns t rc [14] t rc read cycle time 20 25 45 ns t aa [15] t aa address access time 20 25 45 ns t doe t oe output enable to data valid 10 12 20 ns t oha [15] t oh output hold after address change 3 3 3 ns t lzce [16] t lz chip enable to output active 3 3 3 ns t hzce [16] t hz chip disable to output inactive 8 10 15 ns t lzoe [16] t olz output enable to output active 0 0 0 ns t hzoe [16] t ohz output disable to output inactive 8 10 15 ns t pu [13] t pa chip enable to power active 0 0 0 ns t pd [13] t ps chip disable to power standby 20 25 45 ns t dbe - byte enable to data valid 10 12 20 ns t lzbe - byte enable to output active 0 0 0 ns t hzbe - byte disable to output inactive 8 10 15 ns sram write cycle t wc t wc write cycle time 20 25 45 ns t pwe t wp write pulse width 15 20 30 ns t sce t cw chip enable to end of write 15 20 30 ns t sd t dw data setup to end of write 8 10 15 ns t hd t dh data hold after end of write 0 0 0 ns t aw t aw address setup to end of write 15 20 30 ns t sa t as address setup to start of write 0 0 0 ns t ha t wr address hold after end of write 0 0 0 ns t hzwe [16,17] t wz write enable to output disable 8 10 15 ns t lzwe [16] t ow output active after end of write 3 3 3 ns t bw - byte enable to end of write 15 20 30 ns switching waveforms figure 6. sram read cycle #1: address controlled [ 14, 15, 18] $gguhvv 'dwd2xwsxw $gguhvv9dolg 3uhylrxv'dwd9dolg 2xwsxw'dwd9dolg w 5& w $$ w 2+$ notes 14. we must be high during sram read cycles. 15. device is continuously selected with ce , oe and bhe / ble low. 16. measured 200 mv from steady state output voltage. 17. if we is low when ce goes low, the outputs remain in the high impedance state. 18. hsb must remain high during read and write cycles. [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 10 of 25 figure 7. sram read cycle #2: ce and oe controlled [3, 14, 18] figure 8. sram write cycle #1: we controlled [3, 17, 18, 19] $gguhvv9dolg $gguhvv 'dwd2xwsxw 2xwsxw'dwd9dolg 6wdqge\ $fwlyh +ljk,pshgdqfh &( 2( %+(%/( , && w +=&( w 5& w $&( w $$ w /=&( w '2( w /=2( w '%( w /=%( w 38 w 3' w +=%( w +=2( 'dwd2xwsxw 'dwd,qsxw ,qsxw'dwd9dolg +ljk,pshgdqfh $gguhvv9dolg $gguhvv 3uhylrxv'dwd w :& w 6&( w +$ w %: w $: w 3:( w 6$ w 6' w +' w +=:( w /=:( :( %+(%/( &( notes 19. ce or we must be > v ih during address transitions. [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 11 of 25 figure 9. sram write cycle #2: ce controlled [3, 17, 18, 19] figure 10. sram write cycle #3: bhe and ble controlled [3, 17, 18, 19] 'dwd2xwsxw 'dwd,qsxw ,qsxw'dwd9dolg +ljk,pshgdqfh $gguhvv9dolg $gguhvv w :& w 6' w +' %+(%/( :( &( w 6&( w 6$ w %: w +$ w $: w 3:( 'dwd2xwsxw 'dwd,qsxw ,qsxw'dwd9dolg +ljk,pshgdqfh $gguhvv9dolg $gguhvv w :& w 6' w +' %+(%/( :( &( w 6&( w 6$ w %: w +$ w $: w 3:( [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 12 of 25 autostore/power up recall parameters description 20ns 25ns 45ns unit min max min max min max t hrecall [20] power up recall duration 20 20 20 ms t store [21] store cycle duration 8 8 8 ms t delay [22] time allowed to complete sram cycle 20 25 25 ns v switch low voltage trigger level 2.65 2.65 2.65 v t vccrise vcc rise time 150 150 150 s v hdis [13] hsb output driver disable voltage 1.9 1.9 1.9 v t lzhsb hsb to output active time 5 5 5 s t hhhd hsb high active time 500 500 500 ns switching waveforms figure 11. autostore or power up recall [23] 9 6:,7&+ 9 +',6 9 9&&5,6( w 6725( w 6725( w +++' w +++' w '(/$< w '(/$< w /=+6% w /=+6% w +5(&$// w +5(&$// +6%287 $xwrvwruh 32:(5 83 5(&$// 5hdg :ulwh ,qklelwhg 5:, 32:(583 5(&$// 5hdg :ulwh %52:1 287 $xwrvwruh 32:(583 5(&$// 5hdg :ulwh 32:(5 '2:1 $xwrvwruh 1rwh 1rwh 1rwh notes 20. t hrecall starts from the time v cc rises above v switch. 21. if an sram write has not taken place since the last nonvolatile cycle, no autostore or hardware store takes place. 22. on a hardware store, software store / recall, autostore enable / disable and autostore initiation, sram operation continues to be enabled for time t delay . 23. read and wr ite cycles are ignored during store, recall, and while vcc is below v switch. 24. hsb pin is driven high to vcc only by internal 100kohm resistor, hsb driver is disabled. [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 13 of 25 software controlled store/recall cycle in the following table, the so ftware controlled store/recall cycle parameters are listed. [25, 26] parameters description 20 ns 25 ns 45 ns unit min max min max min max t rc store/recall initiation cycle time 20 25 45 ns t sa address setup time 0 0 0 ns t cw clock pulse width 15 20 30 ns t ha address hold time 0 0 0 ns t recall recall duration 200 200 200 s switching waveforms figure 12. ce and oe controlled software store/recall cycle [26] figure 13. autostore enable / disable cycle w 5& w 5& w 6$ w &: w &: w 6$ w +$ w /=&( w +=&( w +$ w +$ w +$ w '(/$< w 6725( w 5(&$// w +++' w /=+6% +ljk,pshgdqfh $gguhvv $gguhvv $gguhvv &( 2( +6%6725(rqo\ '4'$7$ 5:, w 5& w 5& w 6$ w &: w &: w 6$ w +$ w /=&( w +=&( w +$ w +$ w +$ w '(/$< $gguhvv $gguhvv $gguhvv &( 2( '4'$7$ 5:, w 66 notes 25. the software sequence is clocked with ce controlled or oe controlled reads. 26. the six consecutive addr esses must be read in the order listed in table 1 on page 5. we must be high during a ll six consecutive cycles. [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 14 of 25 hardware store cycle parameters description 20ns 25ns 45ns unit min max min max min max t dhsb hsb to output active time when write latch not set 20 25 25 ns t phsb hardware store pulse width 15 15 15 ns t ss [27, 28] soft sequence processing time 100 100 100 s switching waveforms figure 14. hardware store cycle [21] figure 15. soft sequence processing [27, 28] w 3+6% w 3+6% w '(/$< w '+6% w '(/$< w 6725( w +++' w /=+6% :ulwhodwfkvhw :ulwhodwfkqrwvhw +6%,1 +6%287 '4'dwd2xw 5:, +6%,1 +6%287 5:, +6%slqlvgulyhqkljkwr9 && rqo\e\,qwhuqdo 65$0lvglvdeohgdvorqjdv+6%,1lvgulyhqorz +6%gulyhulvglvdeohg w '+6% n2kpuhvlvwru $gguhvv $gguhvv $gguhvv $gguhvv 6riw6htxhqfh &rppdqg w 66 w 66 &( $gguhvv 9 && w 6$ w &: 6riw6htxhqfh &rppdqg w &: notes 27. this is the amount of time it takes to take action on a soft sequence command. vcc power must re main high to effectively reg ister command. 28. commands such as store and recall lock out io until operation is complete which further increases this time. see the specifi c command. [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 15 of 25 truth table for sram operations hsb should remain high for sram operations. for x8 configuration ce we oe inputs/outputs [2] mode power h x x high z deselect/power down standby l h l data out (dq 0 ?dq 7 ); read active l h h high z output disabled active l l x data in (dq 0 ?dq 7 ); write active for x16 configuration ce we oe bhe ble inputs/outputs [2] mode power h x x x x high-z deselect/power down standby l x x h h high-z output disabled active l h l l l data out (dq 0 ?dq 15 ) read active lhlhldata out (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z read active l h l l h data out (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z read active l h h l l high-z output disabled active l h h h l high-z output disabled active l h h l h high-z output disabled active l l x l l data in (dq 0 ?dq 15 ) write active l l x h l data in (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z write active l l x l h data in (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z write active [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 16 of 25 ordering information speed (ns) ordering code package diagram package type operating range 20 cy14b104l-ZS20Xct 51-85087 44-pin tsop ii commercial cy14b104l-ZS20Xit 51-85087 44-pin tsop ii industrial cy14b104l-ZS20Xi 51-85087 44-pin tsop ii cy14b104l-ba20xct 51-85128 48-ball fbga commercial cy14b104l-ba20xit 51-85128 48-ball fbga industrial cy14b104l-ba20xi 51-85128 48-ball fbga cy14b104l-zsp20xct 51-85160 54-pin tsop ii commercial cy14b104l-zsp20xit 51-85160 54-pin tsop ii industrial cy14b104l-zsp20xi 51-85160 54-pin tsop ii cy14b104n-ZS20Xct 51-85087 44-pin tsop ii commercial cy14b104n-ZS20Xit 51-85087 44-pin tsop ii industrial cy14b104n-ZS20Xi 51-85087 44-pin tsop ii cy14b104n-ba20xct 51-85128 48-ball fbga commercial cy14b104n-ba20xit 51-85128 48-ball fbga industrial cy14b104n-ba20xi 51-85128 48-ball fbga cy14b104n-zsp20xct 51-85160 54-pin tsop ii commercial cy14b104n-zsp20xit 51-85160 54-pin tsop ii industrial cy14b104n-zsp20xi 51-85160 54-pin tsop ii 25 cy14b104l-zs25xct 51-85087 44-pin tsop ii commercial cy14b104l-zs25xit 51-85087 44-pin tsop ii industrial cy14b104l-zs25xi 51-85087 44-pin tsop ii cy14b104l-ba25xit 51-85128 48-ball fbga industrial cy14b104l-ba25xi 51-85128 48-ball fbga cy14b104n-ba25xct 51-85128 48-ball fbga commercial cy14b104l-zsp25xct 51-85160 54-pin tsop ii commercial cy14b104l-zsp25xit 51-85160 54-pin tsop ii industrial cy14b104l-zsp25xi 51-85160 54-pin tsop ii cy14b104n-zs25xct 51-85087 44-pin tsop ii commercial cy14b104n-zs25xit 51-85087 44-pin tsop ii industrial cy14b104n-zs25xi 51-85087 44-pin tsop ii cy14b104n-ba25xct 51-85128 48-ball fbga commercial cy14b104n-ba25xit 51-85128 48-ball fbga industrial cy14b104n-ba25xi 51-85128 48-ball fbga cy14b104n-zsp25xct 51-85160 54-pin tsop ii commercial cy14b104n-zsp25xit 51-85160 54-pin tsop ii industrial cy14b104n-zsp25xi 51-85160 54-pin tsop ii [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 17 of 25 45 cy14b104l-zs45xct 51-85087 44-pin tsop ii commercial cy14b104l-zs45xit 51-85087 44-pin tsop ii industrial cy14b104l-zs45xi 51-85087 44-pin tsop ii cy14b104l-ba45xct 51-85128 48-ball fbga commercial cy14b104l-ba45xit 51-85128 48-ball fbga industrial cy14b104l-ba45xi 51-85128 48-ball fbga cy14b104l-zsp45xct 51-85160 54-pin tsop ii commercial cy14b104l-zsp45xit 51-85160 54-pin tsop ii industrial cy14b104l-zsp45xi 51-85160 54-pin tsop ii cy14b104n-zs45xct 51-85087 44-pin tsop ii commercial cy14b104n-zs45xit 51-85087 44-pin tsop ii industrial cy14b104n-zs45xi 51-85087 44-pin tsop ii cy14b104n-ba45xct 51-85128 48-ball fbga commercial cy14b104n-ba45xit 51-85128 48-ball fbga industrial cy14b104n-ba45xi 51-85128 48-ball fbga cy14b104n-zsp45xct 51-85160 54-pin tsop ii commercial cy14b104n-zsp45xit 51-85160 54-pin tsop ii industrial cy14b104n-zsp45xi 51-85160 54-pin tsop ii all parts are pb-free. the above table contains preliminary info rmation. please contact your lo cal cypress sales representative for availability of these parts. ordering information (continued) speed (ns) ordering code package diagram package type operating range [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 18 of 25 part numbering nomenclature option: t - tape & reel blank - std. speed: 20 - 20 ns 25 - 25 ns data bus: l - x8 n - x16 density: 104 - 4 mb voltage: b - 3.0v cypress cy 14 b 104 l - zs p 20 x c t nvsram 14 - auto store + software store + hardware store temperature: c - commercial (0 to 70c) i - industrial (?40 to 85c) pb-free package: ba - 48 fbga zs - tsop ii p - 54 pin blank - 44 pin 45 - 45 ns [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 19 of 25 package diagrams figure 16. 44-pin tsop ii (51-85087) max min. dimension in mm (inch) 11.938 (0.470) plane seating pin 1 i.d. 44 1 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) ejector pin r g o k e a x s 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) base plane 0.10 (.004) 22 23 top view bottom view 51-85087-*a [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 20 of 25 figure 17. 48-ball fbga - 6 mm x 10 mm x 1.2 mm (51-85128) package diagrams (continued) a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.20 max c seating plane 0.530.05 0.25 c 0.15 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 10.000.10 a 10.000.10 6.000.10 b 1.875 2.625 0.36 51-85128-d [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 21 of 25 figure 18. 54-pin tsop ii (51-85160) package diagrams (continued) 51-85160-** [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 22 of 25 document history page document title: cy14b104l/cy14b104n 4 mbit (512k x 8/256k x 16) nvsram document number: 001-07102 rev. ecn no. submission date orig. of change description of change ** 431039 see ecn tup new data sheet *a 489096 see ecn tup removed 48 ssop package added 48 fbga and 54 tsopii packages updated part numbering nomenclature and ordering information added soft sequence processing time waveform *b 499597 see ecn pci removed 35 ns speed bin added 55 ns speed bin. updated ac table for the same changed ?unlimited? read/write to ?infinit e? read/write features section: changed typical i cc at 200-ns cycle time to 8 ma changed store cycles from 500k to 200k cycles shaded commercial grade in operating range table modified icc/is specs 48 fbga package nomenclature changed from bw to bv modified part nomenclature table. changes reflected in ordering information table *c 517793 see ecn tup removed 55ns speed bin changed pinout for 44tsopii and 54tsopii packages changed i sb to 1ma changed i cc4 to 3ma changed v cap min to 35 f changed v ih max to vcc + 0.5v changed t store to 15ms changed t pwe to 10ns changed t sce to 15ns changed t sd to 5ns changed t aw to 10ns removed t hlbl added timing parameters for bhe and ble - t dbe , t lzbe , t hzbe , t bw removed min specification for vswitch changed t glax to 1ns added t delay max of 70us changed t ss specification from 70us min to 70us max *d 774001 see ecn uha changed the data sheet fr om advance information to preliminary 48 fbga package code changed from bv to ba removed 48 fbga package in x8 configuration in ordering information. changed t dbe to 10ns in 15ns part changed t hzbe in 15ns part to 7ns and in 25ns part to10ns changed t bw in 15ns part to 15ns and in 25ns part to 20ns changed t glax to t ghax changed the value of i cc3 to 25ma changed the value of t aw in 15ns part to15ns changed a 18 and a 19 pins in fbga pin configuration to nc *e 914220 see ecn uha included all the information for 45 ns part in this data sheet [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 23 of 25 *f 1889928 see ecn vsutmp8/aesa added footnotes 1, 2 and 3. updated logic block diagram added 48-fbga (x8) pin diagram changed 8mb address expansion pin from pin 43 to pin 42 for 44-tsop ii (x8). updated pin definitions table. corrected typo in v il min spec changed the value of i cc3 from 25ma to 13ma changed i sb value from 1ma to 2ma rearranging of footnotes. updated ordering information table *g 2267286 see ecn gvch/pyrs added bhe and ble information in pin definitions table updated figure 4 (autostore mode) updated footnote 6 changed i cc2 & i cc4 from 3 ma to 6 ma changed i cc3 from 13 ma to 15 ma changed vcap from 35uf min and 57uf max value to 54uf min and 82uf max value changed i sb from 2 ma to 3 ma added input leakage current (i ix ) for hsb in dc electrical characteristics table corrected typo in t dbe value from 22 ns to 20 ns for 45 ns part corrected typo in t hzbe value from 22 ns to 15 ns for 45 ns part corrected typo in t aw value from 15 ns to 10ns for 15 ns part changed t recall from 100 to 200 us added footnotes 9 and 25; reframed footnote 14 and 21 added footnote 14 to figure 7 (sram write cycle #1) *h 2483627 see ecn gvch/pyrs removed 8 ma typical i cc at 200 ns cycle time in feature section referenced footnote 8 to i cc3 in dc characteristics table changed i cc3 from 15 ma to 35 ma changed vcap minimum value from 54 uf to 61 uf changed t avav to t rc figure 11:changed t sa to t as and t sce to t cw *i 2519319 06/20/08 gvch/pyrs added 20 ns access speed in ?features? added i cc1 for t rc =20 ns for both industrial and commercial temperature grade updated thermal resistance table values for 48-fbga, 44-tsop ii and 54-tsop ii packages added ac switching characteristic s specs for 20 ns access speed added software controlled store/re call cycle specs for 20 ns access speed updated ordering information a nd part numbering nomenclature document title: cy14b104l/cy14b104n 4 mbit (512k x 8/256k x 16) nvsram document number: 001-07102 rev. ecn no. submission date orig. of change description of change [+] feedback
cy14b104l, cy14b104n document #: 001-07102 rev. *k page 24 of 25 *j 2600941 11/04/08 gvch/pyrs removed 15 ns access speed updated logic block diagram updated footnote 1 added footnote 2 and 5 pin definition: updated we , hsb and nc pin description page 4:updated sram read, sram write, autostore operation descrip- tion page 4:updated hardware store operation and hardware recall (pow- er-up) description footnote 1 referenced for mode selection table page 6:updated data protection description maximum ratings: added max. accumulated storage time changed i cc2 from 6ma to 10ma changed i cc4 from 6ma to 5ma changed i sb from 3ma to 5ma updated i cc1, i cc3 , i sb and i oz test conditions changed v cap max value from 82uf to 180uf updated footnote 10 and 11 added footnote 12 added data retention and endurance table updated input rise and fall time in ac test conditions referenced footnote 15 to t oha parameter updated all switching waveforms added figure 10 (sram write cycle:bhe and ble controlled) changed t delay to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively changed t store from 15ms to 8ms added v hdis , t hhhd and t lzhsb parameters updated footnote 21 added footnote 24 software controlled store/re call cycle table: changed t as to t sa changed t ghax to t ha added t dhsb parameter changed t hlhx to t phsb updated t ss from 70us to 100us added truth table for sram operations updated ordering information a nd part numbering nomenclature *k 2612931 11/26/08 aesa removed preliminary from header. document title: cy14b104l/cy14b104n 4 mbit (512k x 8/256k x 16) nvsram document number: 001-07102 rev. ecn no. submission date orig. of change description of change [+] feedback
document #: 001-07102 rev. *k revised november 26, 2008 page 25 of 25 autostore and quantumtrap are registered trademarks of simtek corporation. all products and company names mentioned in this doc ument are the trademarks of their respective holders. cy14b104l, cy14b104n ? cypress semiconductor corporation, 2006-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb [+] feedback

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